Our research mission
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devices In nano-electronics era, continuous scaling of CMOS devices now faces quite formidable obstacles which conventional planar architectures cannot overcome. Various 3-dimensional architectures with better control of electrical channels have been actively studied, and nanowire transistor is the best known candidate. Theses nanowire transistors are also expected to show interesting electron transport phenomena since it is possible to confine electrons in a nano-sized semiconductor. We have been fabricated characterized following types of nanowire transistors using both top-down and bottom-up technologies.
- Si nanowire FETs using full CMOS processes
- Gate-all-around Si nanowire FETs using full CMOS processes
- FETs using bottom-up grown Si nanowires
- FETs using bottom-up grown GaN, InP, ZnO, and Al
- CNT FETs
The transport physics we are looking after in studying these devices are as follows.
- Single electron tunneling
- Resonant tunneling
- Transport through a single impurity
- Ballistic transport
- Shell filling
- Manipulation of quantum states
Nano-functional devices Another important factor of CMOS scaling is that the size of the transistor is literally approaching ¡°the ultimate limit¡± of single atom or single molecule. In that case, the most important factor in the scaling scenario will not be the size of the transistor but the number of functions. Special functions of a device can be obtained by combining semiconductor nanowires with functional molecules. Time-domain manipulation of these functional molecules and read-out by the nanowire will create a new type of electronic devices.